module s_counter (
    clk,
    res,
    s_sum
);
input clk;
input res;
output[3:0] s_sum;

parameter freq = 24;

reg[3:0] s_sum;
reg[23:0] con_t; //24MHz 
reg s_pulse;


always @(posedge clk or negedge res) 
begin
    if (res==0) begin
        con_t<=0;
        s_pulse<=0;
        s_sum<=0;
    end else begin
        if (con_t==freq-1) begin
            con_t<=0;    
            s_pulse<=1;     
        end else begin
            con_t=con_t+1;
            s_pulse<=0;
        end
        
        if (s_pulse==1) begin
            if (s_sum==9) begin
                s_sum<=0;
            end  else begin
                s_sum<=s_sum+1;  
            end
        end 
    end 
end

endmodule

//tb
`timescale 10us/1us
module s_counter_tb ();
reg clk;
reg res;
wire[3:0] s_sum;
s_counter s_counter (
    .clk(clk),
    .res(res),
    .s_sum(s_sum)
);

initial begin
    clk<=0;
    res<=0;
    #100 res<=1;
    #100000 $stop;
end

always #1 clk=~clk;


endmodule